High-sensitivity optical scanning using memory integration

ABSTRACT

An inspection system includes a CMOS integrated circuit having integrally formed thereon an at least two dimensional array of photosensors and providing an inspection output representing an object to be inspected. A defect analyzer is operative to receive the inspection output and to provide a defect report.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional PatentApplication No. 60/299,766, filed Jun. 22, 2001, which is incorporatedherein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to optical scanningsystems and sensors, and specifically to scanning techniques employingtwo dimensional sensor arrays.

BACKGROUND OF THE INVENTION

[0003] Scanner systems for acquiring an image of an object, such as aprinted circuit board, are well known in the arts of imaging andautomated optical inspection. Some conventional scanner systems includesensors comprising a linear array of sensor elements. Other conventionalscanner systems include sensors comprising a two dimensional array ofsensor elements. Some systems employing two-dimensional array of sensorelements have been configured, for example, to operate in a time delayintegration (TDI) mode of operation to acquire and image of an object.Other system employing a two-dimensional array of sensor elements havebeen configured to acquire a sequence of non overlapping images of anobject.

[0004] TDI systems are well known in the art of optical scanning. Insuch systems, a sensor array is scanned over an object, such as aprinted circuit board, by moving either the array or the object in adirection perpendicular to the rows of the array. The scanning speed andan array clock are synchronized so that in each column of the array,multiple sensor elements in sequence capture light from the same pointon the object. Charge is accumulated between rows as the sensor arraypasses over the object so that sensor signals in each column are summedfor each point on the object, thereby providing an image of the objectwith enhanced signal/noise ratio.

[0005] Common TDI sensors are based on charge-coupled device (CCD)technology, which allows the sensor signals to be summed by transferringcharge along each column of the sensory array such that newlyaccumulated charge is added to charge having accumulated in previousrows of the column. Other TDI systems based on photodiode arrays, suchas CMOS sensor arrays, are also known in the art.

[0006] U.S. Pat. Nos. 5,750,985 and 5,909,026, the disclosures of whichare incorporated by reference, both describe sensors that can beemployed in a TDI type arrangement.

[0007] Applicants' copending U.S. patent application, Ser. No.10/141,988, filed on May 10, 2002 and entitled “Optical InspectionSystem Employing a Staring Array Scanner”, the disclosure of which isincorporated by reference, describes an inspection system employing atwo dimensional sensor array.

SUMMARY OF THE INVENTION

[0008] It is an object of some aspects of the present invention toprovide improved systems and methods for automated optical inspection(AOI).

[0009] It is a further object of some aspects of the present inventionto provide improved imaging techniques and devices employing twodimensional sensors.

[0010] In accordance with a broad aspect of the present invention, an atleast two dimensional array of photosensors formed on a CMOS integratedcircuit is employed to acquire images representing an object, such asimages of an electrical circuit. At least partially overlapping imagesare acquired, and pixels in the overlapping images, associated withcorresponding portions of the object, are added together to form acomposite image of the object. The composite image is particularlyuseful, for example, to inspect the object for defects. As used hereinthe term CMOS integrated circuit generally includes any suitableintegrated circuit comprising photosensors, such as photodiodes orphotogates, other than CCD type photosensors.

[0011] In preferred embodiments of the present invention, atwo-dimensional imaging device comprises a two-dimensional sensor arrayand a memory, having cells arranged in rows and columns that correspondto the rows and columns of sensor elements in the array. The array andmemory are configured to operate in a memory integration mode so as toprovide a composite image as the array scans over an object. In eachcycle of the array clock (i.e., each time the sensor array captures animage frame), the signal received by each of the sensor elements isdigitized and added to the value stored in one of the cells of thememory. A dynamic input pointer indicates, for each row of the sensorarray, the row in the memory into which the signals from the sensorelements in that row of the array should be added. The input pointer isadvanced at each cycle of the array clock in such a way that each memorycell receives a sum of signals from multiple sensors in the same columnof the array, captured as the sensors pass over the same point on theobject. A dynamic output pointer is also updated at each cycle toindicate the row of the memory in which integration has been completed,so that the memory integrated signal can be read out.

[0012] This use of dynamic input and output pointers enables the sensorarray, memory and memory integration logic to be efficiently implementedtogether on a single chip, preferably using active pixel CMOS sensorelements. The dynamic pointer scheme also allows the direction ofscanning the array to be reversed simply by reversing the pointerdirection, so that the object can be scanned in a bidirectionalserpentine pattern, for example. This feature is particularly useful inAOI systems.

[0013] In some preferred embodiments of the present invention, thesensor array comprises color filters, so that the memory integratedimage captured by the array and memory comprises a color image.Preferably, the color filters are arranged so that successive rows ofthe array receive light of different colors, typically in a repeatingred-green-blue pattern. Alternatively, the color filters may be arrangedso that successive groups of rows receive light of different colors, forexample, several red rows, followed by several green rows, followed byseveral blue rows. Dynamic input and output pointers are provided foreach color. The dynamic pointer configuration and scan rate of the arrayover the object may be chosen to give either a color memory integratedimage with full resolution, equal to that of a comparable monochromememory integrated image, or a color memory integrated image that hasreduced resolution, but whose throughput (i.e., speed of image capture)is equal to that of a monochrome memory integrated image.

[0014] In some preferred embodiments of the present invention, the twodimensional imager is used in an AOI system, typically for evaluatingcharacteristics of objects such as printed circuit boards, flat paneldisplays, electronic assembly boards, and the like. The features of thememory integrated imager described above enable the system to operate athigh speed and with high sensitivity, in either a monochrome or colorimaging mode.

[0015] The present invention will be more fully understood from thefollowing detailed description of the preferred embodiments thereof,taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1A is a schematic, pictorial illustration of a system forautomated optical inspection (AOI), in accordance with a preferredembodiment of the present invention;

[0017]FIG. 1B is a simplified pictorial illustration that generallyshows the operation of the system of FIG. 1B in accordance with apreferred embodiment of the present invention;

[0018]FIG. 1C is more detailed illustration showing operation of acomposite image generator shown in FIG. 1B;

[0019]FIG. 2 is a block diagram that schematically illustrates a twodimensional imaging device, in accordance with a preferred embodiment ofthe present invention;

[0020]FIG. 3 is a block diagram that schematically shows details of theimaging device of FIG. 2, in accordance with a preferred embodiment ofthe present invention;

[0021]FIG. 4 is a block diagram that schematically illustrates the useof memory pointers in the imaging device of FIG. 2, in accordance with apreferred embodiment of the present invention;

[0022] FIGS. 5-8 are timing diagrams that schematically illustrate theoperation of the device of FIG. 2, in accordance with preferredembodiments of the present invention;

[0023]FIG. 9A is a block diagram that schematically illustrates a sensorarray used in a two-dimensional scanning color imaging device, inaccordance with a preferred embodiment of the present invention;

[0024]FIG. 9B is a block diagram that schematically shows details ofdetector elements and memory cells in the device of FIG. 9A, inaccordance with a preferred embodiment of the present invention;

[0025]FIG. 10 is a block diagram that schematically illustrates detectorelements and memory cells in a color two-dimensional imaging device, inaccordance with another preferred embodiment of the present invention;

[0026]FIG. 11A is a block diagram that schematically illustratesdetector elements and memory cells in a color two-dimensional imagingdevice, in accordance with still another preferred embodiment of thepresent invention; and

[0027]FIGS. 11B and 11C are block diagrams that schematically illustratecontents of memory cells in the imaging device of FIG. 11A.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0028]FIG. 1A is a schematic, pictorial illustration of a system 20 forautomated optical inspection (AOI) of a printed circuit board 22, inaccordance with a preferred embodiment of the present invention. Board22 is shown here by way of example, and system 20 may similarly beadapted for inspection of other objects, such as flat panel displays,printed circuit boards loaded with electronic components, integratedcircuits, interconnect devices and moving webs. As used herein, the termelectrical circuit or board shall generally include any such suitablearticle to be inspected. The principles of the present invention, asdescribed in greater detail hereinbelow, may also be applied in otherareas of digital imaging, such as aerial surveillance.

[0029] System 20 captures images of board 22 using a camera 24, which isbuilt around a CMOS integrated circuit imaging device 26 having an atleast two dimensional array of photosensors integrally formed thereon.In accordance with an embodiment of the invention, imaging device 26 isoperational in a memory integration mode of operation. An objective lens28 forms an image of board 22 on device 26 as camera 24 is scanned overthe surface of the board by a translation stage 32. Preferably, thecamera is scanned over the surface in a bidirectional serpentinepattern, so that the entire surface is imaged by the camera at a desiredlevel of resolution. Alternatively, board 22 may be translated whileholding camera 24 still, or both the board and camera may be translated,typically in mutually-perpendicular directions. A light source (notshown) illuminates board 22 as it is imaged by camera 24, preferably byproviding generally continuous illumination, or by providingnon-continuous illumination that is generally synchronized with a framerate of image frames acquired by imaging device 26.

[0030] A camera control unit 30 regulates the timing and operation ofdevice 26, and passes image data from device 26 to an image processor,or analyzer, 34. The image processor analyzes the image data to locateand identify faults, or defects, in board 22. In accordance with apreferred embodiment of the invention processor 34 comprisescombinations of image processing hardware and software such as are usedin various AOI systems available from Orbotech Ltd. of Yavne, Israel,including the Inspire 9060™ and SK-75™ AOI systems. Alternatively oradditionally, processor 34 may comprise a general-purpose computer withsuitable input circuits and software for this purpose, hard-wired logicand/or a programmable digital signal processor. For each board tested bysystem 20, processor 34 outputs either a notification that the board isacceptable or an indication (such as a map) of a fault or faults foundin the board, via a display 36 or other output interface.

[0031]FIG. 1B is a simplified pictorial illustration that generallyshows the operation of system 20, in accordance with a preferredembodiment of the present invention, and to FIG. 1C which is a moredetailed illustration showing operation of a composite image generatorseen in FIG. 1B. Imaging device 26 comprises an at least two dimensionalarray 40 of photosensors 42 integrally formed on a CMOS integratedcircuit. Imaging device 26 generates an inspection output, typically inthe form of image data 220, which corresponds to an object to beinspected such as board 22. Defect analyzer 234 receives the image datafrom imaging device 26 and provides a defect report 236 reportingdefects on board 22, in response to analyzing the image data 220.

[0032] As seen in FIG. 1B, imaging device 26 is operative to acquire aplurality of images of board 22 during the scanning thereof. Fiverepresentative of sequentially acquired images, designated 240, 242,244, 246 and 248 respectively, are seen in FIG. 1B.

[0033] In accordance with an embodiment of the invention, images 240-248are digital pixel images that are sequentially acquired by imagingdevice 26 during scanning a portion of board 22. Only five images areshown for the sake of simplicity. Typically a much greater number ofimages is acquired. Each of the images 240-248 corresponds to a mutuallyoffset portion of board 22 such that each image of board 22 acquired byimaging device 26 at least partially overlaps another image. The mutualoffset between images may be as small as 1 pixel, although the mutualoffset between images may be greater.

[0034] Thus, as seen in FIG. 1B, image 240 is acquired by imaging device26 in a first image frame. After board 22 advances relative to imagingdevice 26 in the direction of arrow 250 by a distance of 1 pixel, image242 is acquired in a second image frame. After board 22 further advancesrelative to imaging device 26 in the direction of arrow 250 by adistance of 1 pixel, image 244 is acquired in a third frame. After board22 further advances relative to imaging device 26 in the direction ofarrow 250 by a distance of 1 pixel, image 246 is acquired in a fourthframe. After board 22 further advances relative to imaging device 26 inthe direction of arrow 250 by a distance of 1 pixel, image 248 isacquired in a fifth frame. This sequence continues until at leastpartially overlapping images are acquired for an entire portion of board22.

[0035] A composite image generator 252 is operative to combine togethereach of the partially overlapping images generated by array 40, forexample images 240-248, and to supply composite image data 260 toanalyzer 234. The composite image data 260 forms image 220 which has animproved signal/noise ratio compared to images 240-248. Image 220 isused by defect analyzer 234 to detect defects in board 22.

[0036] In accordance with an embodiment of the invention, compositeimage generator 252 is integrally formed on imaging device 26, althoughthis need not be the case. As seen in FIG. 1B, each of images 240-248 isa relatively weak image of board 22, while image 220, which is theresult of combining images 240-248 comprises a significantly strongerimage, as seen by the enhanced darkness of image portions correspondingto conductors 249.

[0037] The operation of composite image generator may be betterunderstood from FIG. 1C. Corresponding pixels 254 in each of images240-248 are added together to enhance pixel strength, that is to sayimprove signal to noise. Pixels 254 in image 242 are added tocorresponding pixels 254 in image 240 to result in first composite image274. It is seen that image 242 is offset relative to image 240 andincludes a sequentially added row of pixels 276. It is noted that forreasons of simplicity of presentation, due to orientation of images inFIG. 1C, the rows are actually seen as being columns. Pixels 254 to theleft of row 276 in first composite image 274 are darker than pixels inrow 276.

[0038] Pixels in image 244 are added to corresponding pixels in firstcomposite image 274 to result in second composite image 278. It is seenthat image 244 is offset relative to first composite image 274 andincludes a sequentially added row of pixels 280. Pixels to the left ofrow 276 in second composite image 278 are darker than pixels in row 276,and pixels in row 276 are darker than pixels in row 280.

[0039] Pixels in image 246 are added to corresponding pixels in secondcomposite image 278 to result in third composite image 282. It is seenthat image 246 is offset relative to second composite image 278 andincludes a sequentially added row of pixels 284. Pixels to the left ofrow 276 in third composite image 282 are darker than pixels in row 276,pixels in row 276 are darker than pixels in row 280, and pixels in row280 are darker than pixels in row 284.

[0040] Pixels in image 248 are added to corresponding pixels in thirdcomposite image 282 to result in fourth composite image 286. It is seenthat image 248 is offset relative to third composite image 282 andincludes a sequentially added row of pixels 288. Pixels to the left ofrow 276 in fourth composite image 286 are darker than pixels in row 276,pixels in row 276 are darker than pixels in row 280, pixels in row 280are darker than pixels in row 284, and pixels in row 284 are darker thanpixels in row 288.

[0041] The above process is continued sequentially until a desiredquantity of corresponding pixels are added together such that a gradientis formed in the composite image. At the end of each frame, line ofpixels comprising the result of adding together a plurality of pixels,is provided as image data 260 (FIG. 1B).

[0042] It is a feature of some embodiments of the present invention thatvalues added together in the respective images 240-248 are digitalvalues. The digital values are provided by at least one A/D converterassociated with photosensors 42. An A/D converter may be associated witheach photosensor 42. Optionally, each A/D converter is associated with aplurality of photosensors 42. For example, each A/D converter isassociated with a row of photosensors.

[0043] Preferred embodiments of the architecture, functionality andoperation of imaging device 26 will be discussed hereinbelow in greaterdetail. In general, it is noted that imaging device 26 includes aplurality of digital registers which are operative to temporarily storethe outputs of the A/D converters, digital memory, typically includingan array of memory cells, storing image data provided by the array ofphotosensors, and a plurality of digital adders operative to add theoutputs of the digital registers to corresponding image data which isstored in the digital memory.

[0044] Moreover, in accordance with embodiments of the invention theadding together of images, such as images 240-248, is performed on thefly on a line by line basis, and composite images are stored in a memoryarray in a wrap-around manner that dynamically changes as each new image240-248 is acquired and added to a previously stored composite image.

[0045] It is noted that images 240-248 seen in FIG. 1B generallycorrespond to images formed on array 40. Typically these images are notstored between the acquisition of successive image frames. As will beappreciated from the following detailed discussion of the operation ofimaging device 26, each line in images 240-248 is retrieved and added toa corresponding line in a previously stored composite image, asdescribed with reference to FIG. 1C.

[0046]FIG. 2 is a block diagram that schematically shows the structureof a memory integration imaging device 26, in accordance with apreferred embodiment of the present invention. Device 26 is preferablyfabricated as a single integrated circuit (IC) chip, most preferablyusing a CMOS process. A sensor array 40 comprises a two-dimensionalmatrix of sensor elements 42, preferably active pixel sensors. In eachframe (i.e., at each cycle of the array clock), each element 42generates a signal proportional to the light intensity incident thereon.The signals are typically read out from the sensor array via columndecoder 54 and digitized by an array 44 of A/D (analog to digital)converters and are then stored temporarily in an array 46 of registers,with one register per column of sensor array 40. Alternatively, sensorelements 42 may comprise digital pixel sensors, as described, forexample, by Kleinfelder et al., in “A 10,000 Frames/s 0.18 μm CMOSDigital Pixel Sensor with Pixel-level Memory,” presented at ISSCC 2001,which is incorporated herein by reference. In this case, the output ofarray 40 is already digitized, and A/D converters 44 are unnecessary.

[0047] The digitized signal values held in register array 46 are summedby an array 48 of adders with corresponding stored values in rows of amemory 50, which typically comprises high-speed static or dynamic randomaccess memory (SRAM or DRAM) or any other suitable type of memory. Theresults of the summation are stored back in the same row of the memory.This read/sum/store operation is typically performed for each cell inmemory 50 once per frame. It is repeated over a predetermined number offrames, each time adding in the signal from a different row in array 40,until the memory cell contains the sum of the signals taken from thepredetermined number of different elements 42 in the same column of thearray. The association of sensor elements with memory cells at eachcycle is controlled by a system of dynamic pointers, as described below.After the required number of summations of values from differentelements 42 have been performed for a given row of memory 50, theresults in that row are read out to an array 52 of output registers.These data are then clocked out of the registers to output ports 56 viaa column decoder 54, for readout to processor 34.

[0048] In a preferred embodiment of the invention, as seen in FIG. 2, arow timing block 58 is responsible for maintaining synchronization ofthe image frame capture and readout by array 40, along with thecorresponding operations of A/D converter array 44, register array 46,adder array 48 and memory 50. The row timing is synchronized with thespeed of scanning camera 24 over board 22, as described below, such thatthose values from elements 42 that are added together at adders 48generally correspond to the same location on a board 22. Block 58controls the location of the dynamic pointers used in selecting the rowsof memory 50 for adding and readout and also includes the memory rowdecoder, in order to achieve a desired effect. Block 58 also controlsrow decoders and drivers 60, for reading out the signals from elements42 row by row in each frame, and for resetting array 40 at the end ofeach frame, via a reset control block 62.

[0049]FIG. 3 is a block diagram showing details of device 26, inaccordance with a preferred embodiment of the present invention. In thissimplified embodiment, it is assumed that array 40 and memory 50 eachcomprise four rows. For each column in array 40, there is acorresponding column of cells in memory 50. For simplicity, only four ofthese columns are shown, as well.

[0050] Each sensor element 42 comprises a photodetector (or photosensor)70, typically a photodiode or photogate, and an active amplifier 72which also includes, for example, a select transistor (not shown). Theamplifiers are triggered by row select lines 74 to read out the chargestored by the corresponding photodetectors to column output lines 76.Photodetectors 70 are preferably designed for low capacitance, in orderto reduce the level of reset thermal (kTC) noise that they generate. Inaccordance with a preferred embodiment, each pixel also comprises areset circuitry (not shown), which is separately controlled by resetcontrol 62. Optionally, each sensor element may comprise a separatecharge storage element, such as a capacitor (not shown), to which chargeis transferred from the photodetector and held until it is read out ofthe array. As a further option, mentioned above, each sensor element maycomprise a built-in A/D converter (not shown). Other means known in theart may also be used to enhance the sensitivity and signal/noise ratioof array 40, such as the use of microlenses, integrated with the array,to focus light received by camera 24 onto photodetector 70 within eachsensor element 42.

[0051] Preferably, A/D converter array 44 comprises one A/D converter 78per column of array 40. Optionally, an A/D converter may be associatedwith each element 42. At each cycle of the row clock generated by rowtiming block 58, converter 78 digitizes the signal from a successiveelement 42 in its corresponding column of array 40. The digitized valueis held in a register 80 in register array 46, until it is summed by anadder 82 with the contents of a selected cell 84 in memory 50. The sumsoutput by adders 82 are written back to the same cells in memory 50 fromwhich the addends were read out. Memory cells 84 are arranged in columnscorresponding to the columns of sensor elements 42 in array 40. In thepresent embodiment, cells 84 are arranged in four rows 86, correspondingto the four rows of elements 42 in array 40. The row whose cells 84 areto be read out for summing by adders 82 at each cycle of the row clockis determined by an input pointer 88. After a complete frame has beenread out of array 40, digitized and summed into the appropriate cells inmemory 50, pointer 88 is advanced to a new position for the next frame.As a result, each cell 84 in memory 50 receives the sum of the signalsgenerated by all four sensor elements 42 in the corresponding column ofarray 40.

[0052] An output pointer 92 is used to indicate the row 86 in memory 50whose cells 84 contain the summed signals from all four of the sensorelements 42 in the corresponding column of array 40. At each cycle ofthe row clock, the contents of these cells are read out to registers 90in output register array 52. After the contents of a row of cells havebeen read out, the cells are reset to zero. Then, during the next frame,input pointer 88 is advanced so that the null contents of these memorycells are summed with the signals from the sensor elements in the firstrow of sensor array 40. In each subsequent frame, the pointers areadvanced, and summations are performed, until the cells again containthe sum of signals from all four rows of the sensor array and can againbe read out. Output pointer 92 is likewise advanced in each frame topoint to the next row of memory 50 that is to be read out.

[0053]FIG. 4 is a block diagram that schematically shows a single column102 of sensor array 40, and a single column 104 of memory 50,illustrating the use of pointers 88 and 92, in accordance with apreferred embodiment of the present invention. In the embodiment shownin the preceding figures, all columns are treated identically, so thatthe example shown here in FIG. 4 is representative of the handling ofthe entire array. An arbitrary object 100 is imaged onto column 102 ofarray 40 in four successive frames, designated a-d respectively. Forclarity of illustration, the object is shown alongside column 102,rather than superimposed on it. The position of the object, which is ina translated location respective of column 102 in each of foursuccessive frames of array 40, is shown by successive bars 100 a, 100 b,100 c and 100 d. It will thus be observed that the array clock of array40 is synchronized with the speed of scanning the array over the object(or moving the object under the array), so that the object advances byone pixel in each successive frame. In other words, a point on object100 that is imaged onto sensor element 42 a in the first frame is imagedonto the next sensor element 42 b in the second frame, and so forth upto element 42 d.

[0054] Input pointer 88 is set in each frame to point to the cell 84 inmemory 50 to which the signal from sensor element 42 a is to be added.The location of the input pointer in each of the four successive frames(corresponding to bars 100 a-d) is shown in FIG. 4 by pointers 88 a, 88b, 88 c and 88 d, respectively. The signals from elements 42 b, 42 c and42 d are written to the succeeding cells in column 104, wrapping aroundback to the top of the column when the last cell (84 d) is reached. Thecorrespondence between sensor elements 42 and memory cells 84 in each ofthe four successive frames is indicated by solid arrows for the firstframe (bar 100 a), dashed arrows in the second frame (bar 100 b),dash-dot arrows in the third frame (bar 100 c), and dotted arrows in thefourth frame (bar 100 d).

[0055] Output pointer 92 is set in each frame to point to the cell 84 inmemory 50 to which the signal from sensor element 42 d is added. Thiscell will contain, after the output of adder 82 is written back to thecell, the sum of the signals from all four of sensor elements 42 a-42 din column 102 for each successive pixel on object 100. The contents ofthis cell can thus be read out to register 90 and then reset to zero.The position of the output pointer in each of the four successive framesis shown in FIG. 4 by pointers 92 a, 92 b, 92 c and 92 d, respectively.When output pointer 92 points to a given cell in one frame, inputpointer 88 will point to that same cell in the next frame. Thus, on thenext cycle of the array clock, the cell will begin to accumulate imagedata from sensor element 42 a captured from a new pixel on the object.

[0056]FIG. 5 is a timing diagram that schematically shows timing signalsassociated with the operation of imaging device 26, in accordance with apreferred embodiment of the present invention. The figure illustratesthe operation of the device over two cycles of the array clock, i.e.,two frames. Each frame begins by resetting sensor array 40, to removeresidual charge from sensor elements 42, and then allowing the sensorelements to integrate charge over the remainder of the frame. Thesignals generated by the sensor elements are read out of array 40 row byrow, for rows 1 through N of the array. The signal values are digitizedand summed into memory 50, as described above.

[0057] After all the summations are complete, the summed data are readout of cells 84 in the row 86 of memory 50 that is indicated by outputpointer 92. Pointers 88 and 92 are then advanced to their positions forthe next frame. As soon as all the rows of array 40 have been read out(even before the pointers are advanced), the array can be reset, and theprocess begun over again.

[0058] Note that because of the order of reading out rows 1 through N ofarray 40, the integration times of the rows are not uniform. Row 1 hasthe shortest integration time, while row N has the longest. (The timingpattern shown in FIG. 5 assumes that sensor elements 42 do not containany internal charge storage structure, such as an additional capacitor,or an internal A/D converter, which would allow the integration times ofall the rows to be equalized.) Since every cell 84 in memory 50 receivesand sums signals from all the sensor elements in the correspondingcolumn of array 40, however, the cumulative integration time is the samefor all pixels scanned by camera 24.

[0059]FIG. 6 is a timing diagram that schematically shows timing signalsassociated with the operation of imaging device 26, in accordance withanother preferred embodiment of the present invention. This embodimentis similar to that shown in FIG. 5, except that now the signal from eachsensor element 42 is read out of array 40 twice in each frame: once inforward sequential order from row 1 to N, and then again in reverseorder from row N to 1. This approach is useful in achieving betteruniformity of pixel response. The readout of sensor elements 42 ispreferably non-destructive, i.e., the signal is read out of each sensorelement without removing the charge from the element until the entirearray is reset.

[0060]FIG. 7 is a timing diagram that schematically shows timing signalsassociated with the operation of imaging device 26, in accordance withyet another preferred embodiment of the present invention. Reading outeach sensor element twice in each frame, as in the preceding embodiment,may reduce the speed of operation of device 26. Therefore, in thepresent embodiment, the direction of reading out the rows alternatesfrom frame to frame: once from row 1 to N, and the next time from row Nto 1. This approach provides improved pixel uniformity withoutcompromising readout speed. Preferably, array 40 comprises an evennumber of rows, in order to ensure uniformity of response over allpoints on object 22.

[0061]FIG. 8 is timing diagram that schematically shows timing signalsassociated with the operation of imaging device 26, in accordance withstill another preferred embodiment of the present invention. In thisembodiment, it is assumed that each sensor element in array 40 comprisesa capacitor, memory cell or other internal component capable of storingits charge or signal value after integration is terminated. Thus, auniform integration period can be set for all the elements of array 40.At the conclusion of the integration period, the charge accumulated bythe photodetectors in all the sensor elements is transferredsimultaneously to the respective internal storage components. Thesignals are then read out of the storage components, digitized (ifnecessary) and summed into memory 50 as described above. Meanwhile, thephotodetectors are reset and begin their next integration period, whilethe processing of the signals from the preceding integration period isgoing on.

[0062] Although the embodiments described up to now are directed tomonochrome imaging, system 20 and imaging device 26 may also be adaptedto capture color images of board 22. One approach for this purpose wouldbe to use colored strobe illumination (not shown), for examplesynchronized with the array clock, in which a different color light(typically red, green or blue) is used to illuminate the board in eachsuccessive frame, or for several successive frames. In order to generatecolor images, memory 50 must be divided into separate sections, forreceiving and integrating the signals corresponding to the differentcolors. Within each section, the data are summed and read out usinginput and output pointers in substantially the same way as describedabove. As another alternative, described below with reference to thefigures that follow, different color filters are applied to separaterows of array 40. Of course, different color filters may also be appliedto separate columns of the sensor array, but this option may be lessdesirable as it necessarily detracts from the resolution of camera 24.

[0063]FIG. 9A is a block diagram that schematically illustrates a sensorarray 106 used in a two dimensional scanning color imaging device, inaccordance with a preferred embodiment of the present invention. Thisdevice is similar in most aspects to device 26, as shown and describedabove, and may be used in camera 24 in place of device 26. Therefore,only the salient differences, having to do specifically with capture ofcolor images, are described here.

[0064] In the preferred embodiment seen in FIG. 9A, the rows of array106 are divided into three groups: rows 110, which are configured tocapture red light; rows 112, which are configured to capture greenlight; and rows 114, which are configured to capture blue light.Typically, each row or group of rows is overlaid by a suitable filter,which passes only the range of wavelengths that the particular row issupposed to detect, as is known in the art. Although each group of rowsshown in FIG. 9A is shown as including three rows, each group mayalternatively contain a larger or smaller number of rows. The number ofrows need not be uniform among the different color groups. For example,a greater number of rows of one color (typically blue or green) can beused to compensate for non-uniform sensitivity of the silicon sensor andto provide enhanced resolution of the overall image. Other colorschemes, having different number of groups or configured to capturedifferent electromagnetic radiation wavelength, may also be used.

[0065]FIG. 9B is a block diagram that schematically shows details ofsensor elements in one column 102 of array 106 and memory cells 84 in acorresponding column 104 in memory 50, illustrating imaging based onarray 106, in accordance with a preferred embodiment of the presentinvention. At the top of the figure, object 100 is shown in each of ninesuccessive positions relative to column 102, labeled stage 1 throughstage 9, in a manner similar to that in which the successive objectpositions are shown above in FIG. 4. Each stage corresponds to asuccessive frame of array 106, i.e., to one cycle of the array clock.Object 100 is divided into pixels labeled I, II, III, . . . , XV, at aresolution corresponding to the resolution of array 106.

[0066] For each of stages I through IV, the figure shows the location ofinput pointers 116 and output pointers 118, along with the summedsignals held in each memory cell 84. Three input pointers and threeoutput pointers are provided, one for each color group. At each stage,the signals from the first red, green and blue pixels (R1, G1 and B1)are read into the memory cells indicated by the respective inputpointers 116. The signals from the remaining pixels in each color groupare summed into the next memory cells in column 104, in a manner similarto that shown in FIG. 4. In this way, after three frames are collectedin the memory (i.e., three stages have passed), a given memory cellcontains the sum of the signals from all three of the sensor elements ina given color group. This cell is indicated for readout by outputpointer 118. Table I below lists the pixels whose color values are readout of column 104 at each stage: TABLE I PIXEL OUTPUT FOR FIG. 9B RedGreen Blue Stage output output output 1 VII IV I 2 VIII V II 3 IX VI III4 X VII IV 5 XI VIII V 6 XII IX VI 7 XIII X VII 8 XIV XI VIII 9 XV XIIIX

[0067] It will be observed that the red, green and blue outputsgenerated by array 106 are out of registration by three rows (amountingto six rows between the red and the blue outputs). The registration canbe easily corrected by adding a six-stage buffer for the red output anda three-stage buffer for the green output. These buffers can be providedin the two-dimensional color scanning imaging device itself or on aseparate chip in camera 24. Alternatively, the registration adjustmentmay be performed by processor 34 without prior buffering.

[0068]FIG. 10 is a block diagram showing detector elements and memorycells in a two-dimensional color scanning imaging device, in accordancewith another preferred embodiment of the present invention. In thisembodiment, red rows 110, green rows 112 and blue rows 114 areinterleaved in cyclic alternation, i.e., RGB/RGB/RGB/RGB. Alternatively,other interleaving patterns may be used, such as RGBG/RGBG, etc. At eachstage of operation of the device, each pixel on object 100 is imagedsimultaneously by a sensor element in each of rows 110, 112 and 114.Therefore, the red, green and blue color images are mutually-registeredwithout the need for buffering. The scanning of the imaging array overthe object and the array clock are timed so that from each frame to thenext, object 100 advances by a distance equivalent to one cyclic groupof rows, i.e., by three sensor elements. As a result, a scanning systembased on this embodiment will have high throughput but low resolutionwhen compared to the embodiment of FIGS. 9A and 9B.

[0069] As in the preceding embodiment, three input pointers 116 areprovided, indicating cells 84 to which the first red, green and bluesensor signals (R1, G1 and B1) are to be written at each stage. Threeoutput pointers 118 indicate the cells from which the summed pixelvalues are to be read out. For the present embodiment, in which the RGBcycle repeats four times, the pointers return to their starting valuesafter four frames, labeled stages 1, 2, 3 and 4, are completed.

[0070]FIGS. 11A, B and C are block diagrams that schematicallyillustrate detector elements and memory cells in a two-dimensional colorscanning imaging device, in accordance with still another preferredembodiment of the present invention. Here, too, as in the precedingembodiment, red, green and blue rows of sensor elements are interleavedin the sensor array, and the output pixel values in all three colors arein mutual registration. In the present embodiment, however, fullresolution is maintained, at the expense of reduced speed and increasedmemory size. An imaging device that is configured to operate in themanner shown in FIGS. 11A-C can be reprogrammed in software (orfirmware) to operate in the mode of FIG. 10, as well, with higherthroughput but reduced resolution.

[0071] The memory in the embodiment of FIGS. 11A-C comprises threecolumns 104 for each column 102 of the sensor array. Preferably, columns104 are organized in three sections of memory cells 84: section 120 inFIG. 11A, section 122 in FIG. 11B and section 124 in FIG. 11C. Thenumber of memory cells in each section is equal to the number of sensorelements in the sensor array. The columns of memory cells in eachsection are configured to collect and buffer the sensor signals from allthree colors of every third pixel in object 100. Thus, in eachsuccessive stage, input pointers 116 for each color shift from onesection to the next so that, for example, the signal from the first bluesensor element (B1) is fed to section 124 in stage 1, section 122 instage 2, and section 120 in stage 3. These signal values belongrespectively to pixel VII (stage 1), pixel VIII (stage 2) and pixel IX(stage 3). The signal values from the subsequent blue sensor elements(B2 and B3) are summed into the memory cells that are displaced by threeand six cells, respectively, from the blue input pointer. The green andred signals are treated similarly. At each stage, one color is fed toeach of the sections. According to this scheme, each of the memory cellsis read from and written to only once in every three stages. During theother two stages, the cell simply holds its previous value. It is notedthat only memory cells that are updated at the respective stage areshown, for clarity.

[0072] At each stage, output pointers 118 indicate three adjacent memorycells 84 to be read out from one of the three sections. The outputpointers alternate from section to section in each cycle. The threecells that are read out in each stage contain the red, green and bluepixel values, respectively, of one of the pixels, which are read out ofthe memory simultaneously. Since buffering is performed in the memoryitself, no external buffering is required. Table II below lists thepixels whose values are read out at each stage: TABLE II PIXEL OUTPUTFOR FIG. 9B Pixel Read from Stage output memory section: 1 I 124 2 II122 3 III 120 4 IV 124 5 V 122 6 VI 120 7 VII 124 8 VIII 122 9 IX 120

[0073] Although the preferred embodiments described above relateparticularly to detection of visible light, the principles of thepresent invention may similarly be adapted for detection of other typesof radiation, and particularly for infrared and ultraviolet light. Thus,the “colors” mentioned above should be interpreted more generally asreferring to different wavelength bands.

[0074] It will thus be appreciated that the preferred embodimentsdescribed above are cited by way of example, and that the presentinvention is not limited to what has been particularly shown anddescribed hereinabove. Rather, the scope of the present inventionincludes both combinations and subcombinations of the various featuresdescribed hereinabove, as well as variations and modifications thereofwhich would occur to persons skilled in the art upon reading theforegoing description and which are not disclosed in the prior art.

1. An inspection system comprising: a CMOS integrated circuit havingintegrally formed thereon an at least two dimensional array ofphotosensors and providing an inspection output representing an objectto be inspected; and a defect analyzer operative to receive saidinspection output and to provide a defect report.
 2. The inspectionsystem claimed claim 1 and further comprising a scanner having a supportassembly supporting said object to be inspected and wherein said CMOSintegrated circuit is operative to acquire a plurality of images of saidobject during scanning thereof.
 3. The inspection system claimed inclaim 2 and wherein said plurality of images comprises a plurality ofdigital images.
 4. The inspection system claimed in claim 2 and whereinsaid plurality of images comprises a first plurality of imagesassociated with a first color spectrum and a second plurality of imagesassociated with a second color spectrum.
 5. The inspection systemclaimed in claim 2 and wherein each image in said plurality of images atleast partially overlaps another image in said plurality of images. 6.The image system claimed in claim 2 and wherein each image in saidplurality of images at least partially overlaps another image in saidplurality of images by a single row of pixels generated by said at leasttwo dimensional array of photosensors.
 7. The inspection system claimedin claim 5 and wherein said CMOS integrated circuit includes a compositeimage generator operative to generate a composite image of said objectby combining said plurality of images.
 8. The inspection system claimedin claim 1 and further comprising an illumination assembly generallycontinuously illuminating said object to be inspected and wherein saidCMOS integrated circuit is operative to acquire multiple images of saidobject during illumination thereof.
 9. The inspection system claimed inclaim 2 and further comprising an illumination assembly generallycontinuously illuminating said object to be inspected and wherein saidCMOS integrated circuit is operative to acquire said plurality of imagesduring illumination of said object.
 10. The inspection system claimed inclaim 5 and further comprising an illumination assembly generallycontinuously illuminating said object to be inspected and wherein saidCMOS integrated circuit is operative to acquire said plurality of imagesduring illumination of said object.
 11. The inspection system claimed inclaim 1 and wherein said CMOS integrated circuit has integrally formedthereon, in addition to said at least two dimensional array ofphotosensors, at least one A/D converter receiving outputs from said atleast two dimensional array of photosensors.
 12. The inspection systemclaimed in claim 11 and wherein said at least one A/D convertercomprises an A/D converter associated with each photosensor in saidarray.
 13. The inspection system claimed in claim 11 and wherein said atleast one A/D converter comprises an A/D converter associated with aplurality of photosensors.
 14. The inspection system claimed in claim 11and wherein said CMOS integrated circuit has additionally integrallyformed thereon a plurality of digital registers temporarily storing theoutputs of said A/D converters.
 15. The inspection system claimed inclaim 14 and wherein said CMOS integrated circuit has additionallyintegrally formed thereon: a digital memory storing image data providedby said array; and a plurality of digital adders adding the outputs ofsaid digital registers to corresponding image data stored in saiddigital memory.
 16. The inspection system claimed in claim 15 andwherein said digital memory comprises an array of digital memory cells.17. The inspection system claimed in claim 15 and wherein said CMOSintegrated circuit comprises timing circuitry associated with saidarray, said adders and said digital memory, said timing circuitrygenerating a sequence of clock cycles.
 18. The inspection system claimedin claim 17 and wherein said CMOS integrated circuit comprises: an inputpointer indicating at each clock cycle a location in said digital memoryat which to add an output of said at least one A/D converters; and anoutput pointer indicating at each clock cycle a location in said digitalmemory from which to retrieve said image data.
 19. The inspection systemclaimed in claim 18 and wherein said clock is operative to change alocation of said input pointer and to change a location of said outputpointer at each clock cycle.
 20. The inspection system claimed in claim7 and further comprising an image analyzer analyzing said compositeimage to determine defects in said object.
 21. The inspection systemclaimed in claim 20 and wherein said object is an electrical circuit.22. A method for manufacturing electrical circuits comprising:depositing a portion of an electrical circuit on a substrate in a givenpattern; and optically inspecting said portion to determine defects insaid portion using an inspection system comprising: a CMOS integratedcircuit having integrally formed thereon an at least two dimensionalarray of photosensors and providing an inspection output representing anelectrical circuit to be inspected; and a defect analyzer operative toreceive said inspection output and to provide a defect report.
 23. Themethod claimed in claim 22 and wherein: said inspection system furthercomprises a scanner having a support assembly supporting said electricalcircuit to be inspected; and said CMOS integrated circuit is operativeto acquire a plurality of images of said electrical circuit duringscanning thereof.
 24. The method claimed in claim 23 and wherein saidplurality of images comprises a plurality of digital images.
 25. Themethod claimed in claim 23 and wherein said plurality of imagescomprises a first plurality of images associated with a first colorspectrum and a second plurality of images associated with a second colorspectrum.
 26. The method claimed in claim 23 and wherein each image insaid plurality of images at least partially overlaps another image insaid plurality of images.
 27. The image system claimed in claim 23 andwherein each image in said plurality of images at least partiallyoverlaps another image in said plurality of images by a single row ofpixels generated by said at least two dimensional array of photosensors.28. The method claimed in claim 26 and wherein: said CMOS integratedcircuit includes a composite image generator operative to generate acomposite image of said electrical circuit by combining said pluralityof images.
 29. The method claimed in claim 22 and wherein saidinspection system further comprises: an illumination assembly generallycontinuously illuminating said electrical circuit to be inspected andwherein said CMOS integrated circuit is operative to acquire multipleimages of said electrical circuit during illumination thereof.
 30. Themethod claimed in claim 23 and wherein: said inspection system furthercomprises an illumination assembly generally continuously illuminatingsaid electrical circuit to be inspected; and said CMOS integratedcircuit is operative to acquire said plurality of images duringillumination of said electrical circuit.
 31. The method claimed in claim26 and wherein: said inspection system further comprises an illuminationassembly generally continuously illuminating said electrical circuit tobe inspected; and said CMOS integrated circuit is operative to acquiresaid plurality of images during illumination of said electrical circuit.32. The method claimed in claim 22 and wherein said CMOS integratedcircuit has integrally formed thereon, in addition to said at least twodimensional array of photosensors, at least one A/D converter receivingoutputs from said at least two dimensional array of photosensors. 33.The method claimed in claim 32 and wherein said at least one A/Dconverter comprises an A/D converter associated with each photosensor insaid array.
 34. The method claimed in claim 32 and wherein said at leastone A/D converter comprises an A/D converter associated with a pluralityof photosensors.
 35. The method claimed in claim 32 and wherein saidCMOS integrated circuit has additionally integrally formed thereon aplurality of digital registers temporarily storing the outputs of saidA/D converters.
 36. The method claimed in claim 35 and wherein said CMOSintegrated circuit has additionally integrally formed thereon: a digitalmemory storing image data provided by said array; and a plurality ofdigital adders adding the outputs of said digital registers tocorresponding image data stored in said digital memory.
 37. The methodclaimed in claim 36 and wherein said digital memory comprises an arrayof digital memory cells.
 38. The method claimed in claim 36 and whereinsaid CMOS integrated circuit comprises timing circuitry associated withsaid array, said adders and said digital memory, said timing circuitrygenerating a sequence of clock cycles.
 39. The method claimed in claim38 and wherein said CMOS integrated circuit includes: an input pointerindicating at each clock cycle a location in said digital memory atwhich to add an output of said at least one A/D converters; and anoutput pointer indicating at each clock cycle a location in said digitalmemory from which to retrieve said image data.
 40. The method claimed inclaim 18 and wherein said clock is operative to change a location ofsaid input pointer and to change a location of said output pointer ateach clock cycle.
 41. An inspection system comprising: an integratedcircuit having formed thereon an at least two dimensional array ofphotosensors and providing a plurality of images, each imagerepresenting a portion of an object to be inspected; a composite imagegenerator digitally adding together said plurality of images andproviding a composite image of said object to be inspected; and a defectanalyzer operative to receive said composite image and to provide adefect report.
 42. The inspection system claimed claim 41 and furthercomprising a scanner having a support assembly supporting said object tobe inspected and wherein said integrated circuit is operative to acquiresaid plurality of images during scanning thereof.
 43. The inspectionsystem claimed in claim 41 and wherein said plurality of imagescomprises a plurality of digital images.
 44. The inspection systemclaimed in claim 41 and wherein each image in said plurality of imagesat least partially overlaps another image in said plurality of images.45. The inspection system claimed in claim 44 and wherein an overlapbetween a first image and a second image comprises at least half of saidsecond image.
 46. The inspection system claimed in claim 44 and whereinan overlap between a first image and a second image comprises all ofsaid second image except for a single row of pixels output by said atleast two dimensional array of photosensors.
 47. The inspection systemclaimed in claim 41 and further comprising an illumination assemblygenerally continuously illuminating said object to be inspected andwherein said integrated circuit is operative to acquire said pluralityof images during illumination thereof.
 48. The inspection system claimedin claim 41 and further comprising an illumination assembly generallynon-continuously illuminating said object to be inspected, and whereinsaid integrated circuit is operative to acquire said plurality of imagesduring non-continuous illumination thereof.
 49. The inspection systemclaimed in claim 48 and wherein said illumination assembly is operativeto provide said non-continuous illumination synchronously with saidintegrated circuit acquiring images of said object.
 50. The inspectionsystem claimed in claim 41 and wherein said integrated circuit hasintegrally formed thereon, in addition to said at least two dimensionalarray of photosensors, at least one A/D converter receiving outputs fromsaid at least two dimensional array of photosensors.
 51. The inspectionsystem claimed in claim 50 and wherein said at least one A/D convertercomprises an A/D converter associated with each photosensor in saidarray.
 52. The inspection system claimed in claim 50 and wherein said atleast one A/D converter comprises an A/D converter associated with aplurality of photosensors.
 53. The inspection system claimed in claim 50and wherein said CMOS integrated circuit has additionally integrallyformed thereon a plurality of digital registers temporarily storing theoutputs of said A/D converters.
 54. The inspection system claimed inclaim 53 and wherein said CMOS integrated circuit has additionallyintegrally formed thereon: a digital memory storing image data providedby said array; and a plurality of digital adders adding the outputs ofsaid digital registers to corresponding image data stored in saiddigital memory.
 55. The inspection system claimed in claim 54 andwherein said digital memory comprises an array of digital memory cells.56. The inspection system claimed in claim 54 and wherein said CMOSintegrated circuit comprises timing circuitry associated with saidarray, said adders and said digital memory, said timing circuitrygenerating a sequence of clock cycles.
 57. The inspection system claimedin claim 56 and wherein said CMOS integrated circuit comprises: an inputpointer indicating at each clock cycle a location in said digital memoryat which to add an output of said at least one A/D converters; and anoutput pointer indicating at each clock cycle a location in said digitalmemory from which to retrieve said image data.
 58. The inspection systemclaimed in claim 57 and wherein said clock is operative to change alocation of said input pointer and to change a location of said outputpointer at each clock cycle.
 59. The inspection system claimed in claim41 and wherein said integrated circuit is a CMOS integrated circuit. 60.The inspection system claimed in claim 41 and wherein said object is anelectrical circuit.
 61. A method for manufacturing electrical circuitscomprising: depositing a portion of an electrical circuit on a substratein a given pattern; and optically inspecting said portion to determinedefects in said portion using an inspection system comprising: anintegrated circuit having formed thereon an at least two dimensionalarray of photosensors and providing a plurality of images, each imagerepresenting a portion of an object to be inspected; a composite imagegenerator digitally adding together said plurality of images andproviding a composite image of said object to be inspected; and a defectanalyzer operative to receive said composite image and to provide adefect report.
 62. The method claimed in claim 61 and wherein saidinspection system further comprises: a scanner having a support assemblysupporting said object to be inspected and wherein said integratedcircuit is operative to acquire said plurality of images during scanningthereof.
 63. The method claimed in claim 61 and wherein said pluralityof images comprises a plurality of digital images.
 64. The methodclaimed in claim 61 and wherein each image in said plurality of imagesat least partially overlaps another image in said plurality of images.65. The method claimed in claim 64 and wherein an overlap between afirst image and a second image comprises at least half of said secondimage.
 66. The method claimed in claim 64 and wherein an overlap betweena first image and a second image comprises all of said second imageexcept for a single row of pixels output by said at least twodimensional array of photosensors.
 67. The method claimed in claim 61and wherein said inspection system further comprises: an illuminationassembly generally continuously illuminating said object to be inspectedand wherein said integrated circuit is operative to acquire saidplurality of images during illumination thereof.
 68. The method claimedin claim 61 and wherein said inspection system further comprises: anillumination assembly generally non-continuously illuminating saidobject to be inspected, and wherein said integrated circuit is operativeto acquire said plurality of images during non-continuous illuminationthereof.
 69. The method claimed in claim 68 and wherein saidillumination assembly is operative to provide said non-continuousillumination synchronously with said integrated circuit acquiring imagesof said object.
 70. The method claimed in claim 61 and wherein saidintegrated circuit has integrally formed thereon, in addition to said atleast two dimensional array of photosensors, at least one A/D converterreceiving outputs from said at least two dimensional array ofphotosensors.
 71. The method claimed in claim 70 and wherein said atleast one A/D converter comprises an A/D converter associated with eachphotosensor in said array.
 72. The method claimed in claim 70 andwherein said at least one A/D converter comprises an A/D converterassociated with a plurality of photosensors.
 73. The method claimed inclaim 70 and wherein said integrated circuit has additionally integrallyformed thereon a plurality of digital registers temporarily storing theoutputs of said A/D converters.
 74. The method claimed in claim 73 andwherein said integrated circuit has additionally integrally formedthereon: a digital memory storing image data provided by said array; anda plurality of digital adders adding the outputs of said digitalregisters to corresponding image data stored in said digital memory. 75.The method claimed in claim 74 and wherein said digital memory comprisesan array of digital memory cells.
 76. The method claimed in claim 74 andwherein said integrated circuit comprises timing circuitry associatedwith said array, said adders and said digital memory, said timingcircuitry generating a sequence of clock cycles.
 77. The method claimedin claim 76 and wherein said integrated circuit further comprises: aninput pointer indicating at each clock cycle a location in said digitalmemory at which to add an output of said at least one A/D converters;and an output pointer indicating at each clock cycle a location in saiddigital memory from which to retrieve said image data.
 78. The methodclaimed in claim 77 and wherein said clock is operative to change alocation of said input pointer and to change a location of said outputpointer at each clock cycle.
 79. The method claimed in claim 61 andwherein said integrated circuit is a CMOS integrated circuit.
 80. Amethod for inspecting objects comprising: acquiring a plurality ofsubstantially overlapping images each representing a portion of anobject to be inspected; digitally adding together said images to providea composite image of said object; and analyzing said composite image todetect defects in said object.
 81. The method claimed in claim 80 andwherein said acquiring comprises acquiring said images with a CMOSintegrated circuit.
 82. The method claimed in claim 80 and wherein saidacquiring comprises acquiring images of an electrical circuit.
 83. Themethod claimed in claim 80 and wherein said acquiring further comprisesilluminating said object using generally continuous illumination. 84.The method claimed in claim 80 and wherein said acquiring furthercomprises: acquiring said images at a frame rate; and illuminating saidobject using generally non-continuous illumination fluctuating at aintensity fluctuation rate synchronized with said frame rate.
 85. Themethod claimed in claim 80 and wherein said digitally adding comprisesconverting an image from an analog format to a digital format.
 86. Themethod claimed in claim 85 and wherein said digitally adding comprises:retrieving a previously acquired image from a memory; digitally adding aportion of a newly acquired image in a digital format to a portion ofsaid previously acquired image; and returning to memory an imageresulting from said digitally adding a portion.
 87. A method formanufacturing electrical circuits comprising: depositing a pattern ofconductors on an electrical circuit substrate; acquiring a plurality ofsubstantially overlapping images each representing a portion of saidpattern; digitally adding together said images to provide a compositeimage of said pattern; and analyzing said composite image to detectdefects in said pattern.
 88. The method claimed in claim 87 and whereinsaid acquiring comprises acquiring said images with a CMOS integratedcircuit.
 89. The method claimed in claim 87 and wherein said acquiringfurther comprises illuminating said electrical circuit substrate usinggenerally continuous illumination.
 90. The method claimed in claim 87and wherein said acquiring further comprises: acquiring said images at aframe rate; and illuminating said electrical circuit substrate usinggenerally non-continuous illumination fluctuating at a intensityfluctuation rate synchronized with said frame rate.
 91. The methodclaimed in claim 87 and wherein said digitally adding comprisesconverting an image from an analog format to a digital format.
 92. Themethod claimed in claim 91 and wherein said digitally adding comprises:retrieving a previously acquired image from a memory; digitally adding aportion of a newly acquired image in a digital format to a portion ofsaid previously acquired image; and returning to memory an imageresulting from said digitally adding a portion.
 93. An imaging systemcomprising: an integrated circuit having formed thereon an at least twodimensional array of photosensors and providing a plurality of images,each image representing a partially overlapping portion of an object tobe imaged; and a composite image generator digitally adding togethersaid plurality of images and providing a composite image of said object.94. The imaging system claimed claim 93 and further comprising a scannerhaving a support assembly supporting said object to be inspected andwherein said integrated circuit is operative to acquire said pluralityof images during scanning thereof.
 95. The imaging system claimed inclaim 93 and wherein said plurality of images comprises a plurality ofdigital images.
 96. The imaging system claimed in claim 93 and whereineach image in said plurality of images at least partially overlapsanother image in said plurality of images.
 97. The imaging systemclaimed in claim 96 and wherein an overlap between a first image and asecond image comprises at least half of said second image.
 98. Theimaging system claimed in claim 96 and wherein an overlap between afirst image and a second image comprises all of said second image exceptfor a single row of pixels output by said at least two dimensional arrayof photosensors.
 99. The imaging system claimed in claim 93 and furthercomprising an illumination assembly generally continuously illuminatingsaid object to be imaged and wherein said integrated circuit isoperative to acquire said plurality of images during illuminationthereof.
 100. The imaging system claimed in claim 93 and furthercomprising an illumination assembly generally non-continuouslyilluminating said object to be imaged, and wherein said integratedcircuit is operative to acquire said plurality of images duringnon-continuous illumination thereof.
 101. The imaging system claimed inclaim 100 and wherein said illumination assembly is operative to providesaid non-continuous illumination synchronously with said integratedcircuit acquiring images of said object.
 102. The imaging system claimedin claim 93 and wherein said integrated circuit has integrally formedthereon, in addition to said at least two dimensional array ofphotosensors, at least one A/D converter receiving outputs from said atleast two dimensional array of photosensors.
 103. The imaging systemclaimed in claim 102 and wherein said at least one A/D convertercomprises an A/D converter associated with each photosensor in saidarray.
 104. The imaging system claimed in claim 102 and wherein said atleast one A/D converter comprises an A/D converter associated with aplurality of photosensors.
 105. The imaging system claimed in claim 102and wherein said integrated circuit has additionally integrally formedthereon a plurality of digital registers temporarily storing the outputsof said A/D converters.
 106. The imaging system claimed in claim 105 andwherein said integrated circuit has additionally integrally formedthereon: a digital memory storing image data provided by said array; anda plurality of digital adders adding the outputs of said digitalregisters to corresponding image data stored in said digital memory.107. The imaging system claimed in claim 106 and wherein said digitalmemory comprises an array of digital memory cells.
 108. The imagingsystem claimed in claim 106 and wherein said integrated circuitcomprises timing circuitry associated with said array, said adders andsaid digital memory, said timing circuitry generating a sequence ofclock cycles.
 109. The imaging system claimed in claim 108 and whereinsaid integrated circuit comprises: an input pointer indicating at eachclock cycle a location in said digital memory at which to add an outputof said at least one A/D converters; and an output pointer indicating ateach clock cycle a location in said digital memory from which toretrieve said image data.
 110. The imaging system claimed in claim 109and wherein said clock is operative to change a location of said inputpointer and to change a location of said output pointer at each clockcycle.
 111. The imaging system claimed in claim 93 and wherein saidintegrated circuit is a CMOS integrated circuit.
 112. The imaging systemclaimed in claim 93 and wherein said object is an electrical circuit.113. A method for imaging objects comprising: acquiring a plurality ofsubstantially overlapping images each representing a portion of anobject to be imaged; and digitally adding together said images toprovide a composite image of said object.
 114. The method claimed inclaim 113 and wherein said acquiring comprises scanning an at least twodimensional array of photosensors relative to said object.
 115. Themethod claimed in claim 114 and wherein said acquiring comprisesacquiring said images using an at least two dimensional array ofphotosensors disposed on a CMOS integrated circuit.
 116. The methodclaimed in claim 113 and wherein said acquiring comprises acquiring saidimages using an at least two dimensional array of photosensors disposedon a CMOS integrated circuit.
 117. The method claimed in claim 113 andwherein said acquiring comprises acquiring images of an electricalcircuit.
 118. The method claimed in claim 113 and wherein said acquiringfurther comprises illuminating said object using generally continuousillumination.
 119. The method claimed in claim 113 and wherein saidacquiring further comprises: acquiring said images at a frame rate; andilluminating said object using generally non-continuous illuminationfluctuating at an intensity fluctuation rate synchronized with saidframe rate.
 120. The method claimed in claim 113 and wherein saiddigitally adding comprises converting an image from an analog format toa digital format.
 121. The method claimed in claim 120 and wherein saiddigitally adding comprises: retrieving a previously acquired image froma memory; digitally adding a portion of a newly acquired image in adigital format to a portion of said previously acquired image; andreturning to memory an image resulting from said digitally adding aportion.
 122. A single chip integrated circuit suitable for use in animaging system and comprising: a CMOS integrated circuit havingintegrally formed thereon: an at least two dimensional array ofphotosensors; at least one A/D converter receiving outputs from said atleast two dimensional array of photosensors; a plurality of digitalregisters temporarily storing the outputs of said A/D converters; adigital memory storing image data provided by said array; and aplurality of digital adders adding the outputs of said digital registersto corresponding image data stored in said digital memory.
 123. Thesingle chip integrated circuit claimed in claim 122 and wherein said atleast one A/D converter comprises an A/D converter associated with eachphotosensor in said array.
 124. The single chip integrated circuitclaimed in claim 122 and wherein said at least one A/D convertercomprises an A/D converter associated with a plurality of photosensors.125. The single chip integrated circuit claimed in claim 122 and whereinsaid digital memory comprises an array of digital memory cells.
 126. Thesingle chip integrated circuit claimed in claim 122 and furthercomprising timing circuitry associated with said array, said adders andsaid digital memory, said timing circuitry generating a sequence ofclock cycles.
 127. The single chip integrated circuit claimed in claim126 and further comprising: an input pointer indicating at each clockcycle a location in said digital memory at which to add an output ofsaid at least one A/D converters; and an output pointer indicating ateach clock cycle a location in said digital memory from which toretrieve said image data.
 128. The single chip integrated circuitclaimed in claim 127 and wherein said clock is operative to change alocation of said input pointer and to change a location of said outputpointer at each clock cycle.
 129. An imaging device, comprising: anarray of sensor elements, arranged in a matrix of sensor rows and sensorcolumns, each such sensor element being adapted to output a signalresponsive to radiation incident thereon; a memory, comprising memorycells arranged in memory rows and memory columns, each such memory cellbeing adapted to store a signal value; one or more adders, adapted tosum the signal output by the sensing elements with the signal valuestored in the memory cells; and timing circuitry, coupled to control thearray, memory and adders, and adapted to generate an input pointer andan array clock having clock cycles, such that at each cycle of the arrayclock, the signal from the sensor elements in each of the sensor rows issummed by the adders with the stored signal value in the cells in arespective one of the memory rows that is determined by the inputpointer, thus generating summed signal values that are stored in thememory cells, the timing circuitry further being adapted to advance theinput pointer in successive cycles of the array clock so that the summedsignal value stored in each of the memory cells comprises a sum of thesignals output by a plurality of the sensing elements in a given one ofthe sensor columns.
 130. A device according to claim 129, wherein thetiming circuitry is further adapted to generate an output pointer and toadvance the output pointer in the successive cycles of the array clockso that at each cycle of the array clock, the summed signal values areread out of the cells in one of the memory rows that is indicated by theoutput pointer.
 131. A device according to claim 130, wherein the timingcircuitry is adapted to control the input and output pointers so thatthe summed signal values read out at each cycle of the array clock aresummed over a predetermined number of the sensor elements.
 132. A deviceaccording to claim 130, wherein the radiation incident on the sensorelements is received from an object that is in motion relative to thedevice, and wherein the timing circuitry is adapted to generate thearray clock in synchronization with the motion, so that the summedsignal values read out of the cells make up an image of the object. 133.A device according to claim 132, wherein the timing circuitry is adaptedto select a direction in which to advance the input and output pointersin the successive cycles of the array clock responsive to the directionof the motion.
 134. A device according to claim 129, wherein the sensorrows are arranged in a row order from a first row to a last row in thearray, and wherein the timing circuitry is adapted to control the arrayso that the signal is read out of the array both in a first readoutorder beginning from the first row and in a second readout orderbeginning from the last row.
 135. A device according to claim 134,wherein the timing circuitry is adapted to control the array so that thesignal is read out in the first and second readout orders inalternation.
 136. A device according to claim 129, wherein the timingcircuitry is controllable so as to vary a direction in which the inputpointer is advanced from each of the memory rows to its neighboring rowin each of the clock cycles.
 137. A device according to claim 129,wherein the sensor elements comprise CMOS sensor elements.
 138. A deviceaccording to claim 137, wherein the CMOS sensor elements comprise activepixel sensors.
 139. A device according to claim 137, wherein the array,memory, adders and timing circuitry are fabricated together on a singleintegrated circuit chip.
 140. A device according to claim 129, andcomprising a multiplicity of analog/digital (A/D) converters, each suchA/D converter coupled to receive and digitize the signal from the sensorelements in a respective one of the sensor columns, and to output thedigitized signal to a corresponding one of the adders.
 141. A deviceaccording to claim 140, wherein each of the adders is coupled to outputthe summed signal values to the memory cells in a corresponding one ofthe memory columns.
 142. A device according to claim 129, wherein thesensor elements in each of the sensor rows are adapted to output thesignal responsive to radiation incident thereon in a respectivewavelength band, selected from among multiple wavelength bands that thearray is configured to receive.
 143. An imaging device, comprising: anarray of sensor elements, arranged in a matrix of sensor rows and sensorcolumns, each such sensor element being adapted to output a signalresponsive to radiation incident thereon in a respective wavelengthband, selected from among multiple wavelength bands that the array isconfigured to receive; a memory, comprising memory cells arranged inmemory rows and memory columns, each such memory cell being adapted tostore a signal value; one or more adders, adapted to sum the signaloutput by the sensing elements with the signal value stored in thememory cells; and timing circuitry, coupled to control the array, memoryand adders, and adapted to generate an array clock having clock cycles,such that at each cycle of the array clock, the signal from each of thesensor elements is summed by the adders with the stored signal value ina designated one of the memory cells, thus generating summed signalvalues that are stored in the memory cells, each of the summed signalvalues comprising a sum of the signals output by a plurality of thesensor elements in a given one of the sensor columns responsive to theradiation in one of the multiple wavelength bands, such that differentones of the memory cells contain the summed signal values for different,respective wavelength bands.
 144. A device according to claim 143,wherein the sensor elements in each of the sensor rows are adapted tooutput the signal responsive to the radiation incident thereon in thesame respective wavelength band.
 145. A device according to claim 144,wherein the timing circuitry is adapted to generate an input pointer foreach of the wavelength bands, such that at each cycle of the arrayclock, the signal from the sensor elements in each of the sensor rows issummed by the adders with the stored signal value in the cells in arespective one of the memory rows that is determined by the inputpointer for the respective wavelength band.
 146. A device according toclaim 145, wherein the timing circuitry is adapted to advance the inputpointer for each of the wavelength bands in successive cycles of thearray clock so that the summed signal value stored in each of the memorycells comprises a sum of the signals output by a plurality of thesensing elements in a given one of the sensor columns.
 147. A deviceaccording to claim 146, wherein the timing circuitry is further adaptedto generate an output pointer for each of the wavelength bands and toadvance the output pointer for each of the wavelength bands in thesuccessive cycles of the array clock so that at each cycle of the arrayclock, the summed signal values for each of the wavelength bands areread out of the cells in one of the memory rows that is indicated by theoutput pointer.
 148. A device according to claim 144, wherein the sensorrows are arranged in two or more groups, each of the groups comprisingtwo or more mutually-adjacent rows, such that the sensor elements ineach of the groups are adapted to output the signal responsive to theradiation incident thereon in the same respective wavelength band. 149.A device according to claim 144, wherein the sensor rows are arranged sothat each of the sensor rows has a different respective wavelength bandfrom the other sensor rows that are adjacent to it.
 150. A deviceaccording to claim 149, wherein the radiation incident on the sensorelements is received from an object, and wherein the summed signalvalues make up a multiple-wavelength image of the object, and whereinthe timing circuitry is adapted to control the array so that the sensorelements in two or more of the adjacent sensor rows receive theradiation from a common point on the object simultaneously during one ofthe clock cycles.
 151. A device according to claim 149, wherein theradiation incident on the sensor elements is received from an object,and wherein the summed signal values make up a multiple-wavelength imageof the object, and wherein the timing circuitry is adapted to controlthe array so that the sensor elements in the adjacent sensor rowsreceive the radiation from a given point on the object in successiveclock cycles.
 152. A device according to claim 143, wherein theradiation incident on the sensor elements is received from an objectthat is in motion relative to the device, and wherein the timingcircuitry is adapted to generate the array clock in synchronization withthe motion, so that the summed signal values read out of the cells makeup an image of the object.
 153. A device according to claim 143, whereinthe sensor elements comprise CMOS sensor elements.
 154. A deviceaccording to claim 153, wherein the CMOS sensor elements comprise activepixel sensors.
 155. A device according to claim 153, wherein the array,memory, adders and timing circuitry are fabricated together on a singleintegrated circuit chip.
 156. Apparatus for automated optical inspectionof an object, comprising: an imaging device, which comprises: an arrayof sensor elements, arranged in a matrix of sensor rows and sensorcolumns, each such sensor element being adapted to output a signalresponsive to radiation from the object that is incident thereon; amemory, comprising memory cells arranged in memory rows and memorycolumns, each such memory cell being adapted to store a signal value;one or more adders, adapted to sum the signal output by the sensingelements with the signal value stored in the memory cells; and timingcircuitry, coupled to control the array, memory and adders, and adaptedto generate an input pointer and an array clock having clock cycles,such that at each cycle of the array clock, the signal from the sensorelements in each of the sensor rows is summed by the adders with thestored signal value in the cells in a respective one of the memory rowsthat is determined by the input pointer, thus generating summed signalvalues that are stored in the memory cells, the summed signal valuescorresponding to pixels in an image of the object, the timing circuitryfurther being adapted to advance the input pointer in successive cyclesof the array clock so that the summed signal value stored in each of thememory cells comprises a sum of the signals output by a plurality of thesensing elements in a given one of the sensor columns; a scanningdevice, adapted to impart translational motion to at least one of theimaging device and the object, causing the imaging device to scan overthe object while the radiation is incident on the sensor elements, andwhile the device operates to generate the summed signal values; and animage processor, coupled to receive the summed signal values from thememory and to analyze the values so as to evaluate a characteristic ofthe object.
 157. Apparatus according to claim 156, wherein the timingcircuitry is adapted to generate the array clock in synchronization withthe translational motion.
 158. Apparatus according to claim 156, whereinthe scanning device is adapted to cause the imaging device to scan overthe object in first and second opposing directions, parallel to thesensor columns, and wherein the timing circuitry is adapted to select adirection in which to advance the input pointer in the successive cyclesof the array clock responsive to the direction of the scan. 159.Apparatus for automated optical inspection of an object, comprising: animaging device, comprising: an array of sensor elements, arranged in amatrix of sensor rows and sensor columns, each such sensor element beingadapted to output a signal responsive to radiation from the object thatis incident thereon in a respective wavelength band, selected frommultiple wavelength bands that the array is configured to receive; amemory, comprising memory cells arranged in memory rows and memorycolumns, each such memory cell being adapted to store a signal value;one or more adders, adapted to sum the signal output by the sensingelements with the signal value stored in the memory cells; and timingcircuitry, coupled to control the array, memory and adders, and adaptedto generate an array clock having clock cycles, such that at each cycleof the array clock, the signal from each of the sensor elements issummed by the adders with the stored signal value in a designated one ofthe memory cells, thus generating summed signal values that are storedin the memory cells, the summed signal values corresponding to pixels inan image of the object, each of the summed signal values comprising asum of the signals output by a plurality of the sensor elements in agiven one of the sensor columns responsive to the radiation in one ofthe multiple wavelength bands, such that different ones of the memorycells contain the summed signal values for different, respectivewavelength bands. a scanning device, adapted to impart translationalmotion to at least one of the imaging device and the object, causing theimaging device to scan over the object while the radiation is incidenton the sensor elements, and while the device operates to generate thesummed signal values; and an image processor, coupled to receive thesummed signal values from the memory and to analyze the values so as toevaluate a characteristic of the object.
 160. A method for imaging,using an array of sensor elements, arranged in a matrix of sensor rowsand sensor columns, each such sensor element being adapted to output asignal responsive to radiation incident thereon, and a memory, whichincludes memory cells arranged in memory rows and memory columns, eachsuch memory cell being adapted to store a signal value, the methodcomprising: generating an array clock having clock cycles and an inputpointer that points to one or more of the memory rows; at each cycle ofthe array clock, summing the signal output by the sensing elements ineach of the sensor rows with the signal value stored in the memory cellsin a respective one of the memory rows that is determined by the inputpointer, thus generating summed signal values that are stored in thememory cells; and advancing the input pointer in successive cycles ofthe array clock so that the summed signal value stored in each of thememory cells comprises a sum of the signals output by a plurality of thesensing elements in a given one of the sensor columns.
 161. A methodaccording to claim 160, and comprising: generating an output pointer; ateach cycle of the array clock, reading out the summed signal values fromthe cells in one of the memory rows that is indicated by the outputpointer; and advancing the output pointer in the successive cycles ofthe array clock.
 162. A method according to claim 161, wherein advancingthe input and output pointers comprises controlling the input and outputpointers so that the summed signal values read out at each cycle of thearray clock are summed over a predetermined number of the sensorelements.
 163. A method according to claim 161, wherein the radiationincident on the sensor elements is received from an object that is inmotion relative to the method, and wherein generating the array clockcomprises synchronizing the array clock with the motion, so that thesummed signal values read out of the cells make up an image of theobject.
 164. A method according to claim 163, wherein advancing theinput and output pointers comprises selecting a direction in which toadvance the input and output pointers in the successive cycles of thearray clock responsive to the direction of the motion.
 165. A methodaccording to claim 160, wherein the sensor rows are arranged in a roworder from a first row to a last row in the array, and wherein summingthe signal output by the sensing elements comprises reading the signalout of the array both in a first readout order beginning from the firstrow and in a second readout order beginning from the last row.
 166. Amethod according to claim 165, wherein reading the signal out of thearray comprises controlling the array so that the signal is read out inthe first and second readout orders in alternation.
 167. A methodaccording to claim 160, wherein advancing the input pointer comprisesvarying a direction in which the input pointer is advanced from each ofthe memory rows to its neighboring row in the successive cycles of thearray clock.
 168. A method according to claim 160, wherein summing thesignal comprises digitizing the signal output by the sensing elementsusing multiple analog/digital (A/D) converters, each such A/D converterreceiving and digitizing the signal from the sensor elements in arespective one of the sensor columns, and summing the digitized signalwith the stored signal value.
 169. A method according to claim 160,wherein the sensor elements in each of the sensor rows are adapted tooutput the signal responsive to radiation incident thereon in arespective wavelength band, selected from among multiple wavelengthbands that the array is configured to receive, and wherein generatingthe summed signal values comprises generating respective summed signalvalues for the multiple wavelength bands.
 170. A method for imaging,using an array of sensor elements, arranged in a matrix of sensor rowsand sensor columns, each such sensor element being adapted to output asignal responsive to radiation incident thereon in a respectivewavelength band, selected from among multiple wavelength bands that thearray is configured to receive, and a memory, which includes memorycells arranged in memory rows and memory columns, each such memory cellbeing adapted to store a signal value, the method comprising: generatingan array clock having clock cycles and an input pointer that points toone or more of the memory rows; and at each cycle of the array clock,summing the signal output by each of the sensing elements with thesignal value stored in a designated one of the memory cells, thusgenerating summed signal values that are stored in the memory cells,each of the summed signal values comprising a sum of the signals outputby a plurality of the sensor elements in a given one of the sensorcolumns responsive to the radiation in one of the multiple wavelengthbands, such that different ones of the memory cells contain the summedsignal values for different, respective wavelength bands.
 171. A methodaccording to claim 170, wherein the sensor elements in each of thesensor rows are adapted to output the signal responsive to the radiationincident thereon in the same respective wavelength band, and comprisinggenerating an input pointer for each of the wavelength bands, whereinsumming the signal comprises summing the signal from the sensor elementsin each of the sensor rows with the stored signal value in the cells ina respective one of the memory rows that is determined by the inputpointer for the respective wavelength band.
 172. A method according toclaim 171, wherein generating the input pointer comprises advancing theinput pointer for each of the wavelength bands in successive cycles ofthe array clock so that the summed signal value stored in each of thememory cells comprises a sum of the signals output by a plurality of thesensing elements in a given one of the sensor columns.
 173. A methodaccording to claim 172, and comprising: generating an output pointer foreach of the wavelength bands; at each cycle of the array clock, readingout the summed signal values for each of the wavelength bands from thecells in one of the memory rows that is indicated by the output pointer;and advancing the output pointer for each of the wavelength bands in thesuccessive cycles of the array clock.
 174. A method according to claim170, wherein the sensor elements in each of the sensor rows are adaptedto output the signal responsive to the radiation incident thereon in thesame respective wavelength band, the sensor rows being arranged in twoor more groups, each of the groups comprising two or moremutually-adjacent rows, such that the sensor elements in each of thegroups are adapted to output the signal responsive to the radiationincident thereon in the same respective wavelength band, and whereinsumming the signal comprises summing the signal output by the sensorelements in the mutually-adjacent rows in each of the groups.
 175. Amethod according to claim 170, wherein the sensor elements in each ofthe sensor rows are adapted to output the signal responsive to theradiation incident thereon in the same respective wavelength band, thesensor rows being arranged so that each of the sensor rows has adifferent respective wavelength band from the other sensor rows that areadjacent to it, and wherein the radiation incident on the sensorelements is received from an object, so that the summed signal valuesmake up a multiple-wavelength image of the object, and whereingenerating the array clock comprises controlling the array so that thesensor elements in two or more of the adjacent sensor rows receive theradiation from a common point on the object simultaneously during one ofthe clock cycles.
 176. A method according to claim 170, wherein thesensor elements in each of the sensor rows are adapted to output thesignal responsive to the radiation incident thereon in the samerespective wavelength band, the sensor rows being arranged so that eachof the sensor rows has a different respective wavelength band from theother sensor rows that are adjacent to it, and wherein the radiationincident on the sensor elements is received from an object, so that thesummed signal values make up a multiple-wavelength image of the object,and wherein generating the array clock comprises controlling the arrayso that the sensor elements in the adjacent sensor rows receive theradiation from a given point on the object in successive clock cycles.177. A method according to claim 170, wherein the radiation incident onthe sensor elements is received from an object that is in motionrelative to the method, and wherein generating the array clock comprisessynchronizing the array clock with the motion, so that the summed signalvalues read out of the cells make up an image of the object.
 178. Amethod for automated optical inspection of an object, comprising:collecting radiation from the object to impinge on an array of sensorelements, arranged in a matrix of sensor rows and sensor columns, eachsuch sensor element being adapted to output a signal responsive to theradiation incident thereon; coupling the array to a memory, whichincludes memory cells arranged in memory rows and memory columns, eachsuch memory cell being adapted to store a signal value; generating anarray clock having clock cycles and an input pointer that points to oneor more of the memory rows; at each cycle of the array clock, summingthe signal output by the sensing elements in each of the sensor rowswith the signal value stored in the memory cells in a respective one ofthe memory rows that is determined by the input pointer, thus generatingsummed signal values that are stored in the memory cells; advancing theinput pointer in successive cycles of the array clock so that the summedsignal value stored in each of the memory cells comprises a sum of thesignals output by a plurality of the sensing elements in a given one ofthe sensor columns; scanning the array over the object while theradiation is incident on the sensor elements, and while generating thearray clock, summing the signal, and advancing the input pointer, togenerate the summed signal values; and receiving and processing thesummed signal values from the memory so as to evaluate a characteristicof the object.
 179. A method according to claim 178, wherein generatingthe array clock comprises synchronizing the array clock with thescanning of the array.
 180. A method according to claim 178, whereinscanning the array comprises reversing a direction of scanning the arrayover the object, and wherein advancing the pointer comprises reversingthe direction of advancing the pointer in the successive cycles of thearray clock responsive to the direction of the scan.
 181. A method forautomated optical inspection of an object, comprising: collectingradiation from the object to impinge on an array of sensor elements,arranged in a matrix of sensor rows and sensor columns, each such sensorelement being adapted to output a signal responsive to the radiationincident thereon in a respective wavelength band, selected from multiplewavelength bands that the array is configured to receive; coupling thearray to a memory, which includes memory cells arranged in memory rowsand memory columns, each such memory cell being adapted to store asignal value; generating an array clock having clock cycles and an inputpointer that points to one or more of the memory rows; and at each cycleof the array clock, summing the signal output by each of the sensingelements with the signal value stored in a designated one of the memorycells, thus generating summed signal values that are stored in thememory cells, each of the summed signal values comprising a sum of thesignals output by a plurality of the sensor elements in a given one ofthe sensor columns responsive to the radiation in one of the multiplewavelength bands, such that different ones of the memory cells containthe summed signal values for different, respective wavelength bands;scanning the array over the object while the radiation is incident onthe sensor elements, and while generating the array clock and summingthe signal to generate the summed signal values; and receiving andprocessing the summed signal values from the memory for the differentwavelength bands so as to e valuate a characteristic of the object.